DEMETER is a European project aiming at answering the needs of the European industry in two
- The programmable logic (FPGA and CPLD) market, which is still one of the fastest growing markets in the semiconductor industry. One of the emerging applications of FPGAs in Europe is in harsh environment market. This market puts severe requirements on FPGAs such as reliability, security, re-configurability and more importantly European Independence.
- The embedded applications in the avionic domain, which are more and more demanding in terms of computing capabilities. This continuous increase of performance can be naturally addressed with multi-core architectures. However, they lead to a certain indeterminism in the software execution that is not compatible with avionic certification constraints. The DEMETER platforms will bring the means to European avionic actors to evaluate the multi cores concept regarding aeronautic certification.
DEMETER had two main objectives related to Space and Avionics domains:
- DEMETER will give a unique opportunity to develop next leading generation of rad-hard FPGA in in 28-FDSOI technology which combine a high level of integration with an outstanding intrinsic radiation robustness. The objective of DEMETER related to rad-hard FPGA is to bring unique innovative solutions by integrating protection through native code, directly on chip and in software ina European pilot line platform delivering circuits free of export control in the whole European Union.The test chip will bring different solutions for a local production of FPGAs with the following requirements:
- Numerous Configurable Logic Blocks, an extensive routing matrix, abundant inputs and outputs, high speed and low power: This is required to enable today’s increasingly demanding applications. IPs will include microprocessors, controllers & DSP cores, Ethernet, high speed communication interfaces, filters, cryptography, etc.
- Ease of use: this encompasses the tools to design and route the FPGA as well as having IPs available and easily re-usable,
- Cryptography and security which will secure: the programming bit-stream of the component,the data content and the intellectual properties implemented in the FPGA, Different approaches will be developed in the frame of DEMETER to assess the sensitivity of integrated circuits against radiative environments in 28 nm technologies and beyond.
- For avionics DEMETER will be providing innovative platforms to produce and demonstrate Systems on Chip that are currently not available on the market. DEMETER will offer a high performance computing platform enabling:
- The evaluation of the multi core concept regarding aeronautic certification.
- The exploration of the architectural possibilities associated with an embedded FPGA offering the capability to implement dedicated logic that is closely coupled to the 64-bit cores.The development of the SW requirements for a better predictability in HW utilization.
- The analysis of the certifiably of hypervisors running on multi-core platform.
- And finally to make recommendations in terms of requirements and architecture for a future SoC.
DEMETER achieved results:
In space domain:
- A standalone FPGA test chip has been developed in 28nm FDSOI technology to remove all thetechnical barriers of the future NG-ULTRA FPGA:
- Radiation hardening: to guarantee the reliability and the extended lifetime of Systems-on-Chip for the targeted harsh environments,
- Cryptography and tamper proof apparatus: to protect data contents and Intellectual property,adapted to various markets (but still ongoing),
- Partial Reconfigurable schemes: in-field fault and failure detection and reparation will be developed; this will enable the manufacturability of high quality and more reliable complex FPGA,
- European technology independency.
- A high performance hardened AES IP core targeting 28nm FD-SOI has been designed.
- Several approaches to assess the sensitivity of integrated circuits against radiative environments in 28nm technologies have been proposed with:
- The creation of 28nm FDSOI “response model” that enable to simulate any design (cell) implemented in this process by using the TFIT tool
- The adaptation of MUSCA SEP3 simulation tools to support hardening design on 28-nm
- The improvement of radiation predictions in order to retain relevant estimates of sensitivity on the most advanced technologies
In avionic domain:
- Evaluation of the multi-core concept regarding aeronautic certification,
- Software layers allowing a fine hardware control and bringing the adequate properties to the multicore SOC to make compliant with aeronautic certification constraints
- Definition of the worst case usage domain for a multi-core ARM® based avionics platform
- Analysis of conceivable solutions to ensure certificability of multi cores COTS based avionics solutions
- Understanding the non-deterministic behaviour of COTS
- Evaluation, selection and/or design of IPs for avionics application, and associated recommendations for architectural choices and IP configuration
- The DEMETER project has allowed ADICSYS to expand its FPGA compilation flow and to render it more flexible while including the end user into the architecture decision process both at the presilicon IP level and the post silicon synthesis and compilation level. In retrospect, this flow improvement appears to be essential to the embedded FPGA concept. Unlike off-the-shelf FPGAsthat are one-fits-all solutions, by its embedded nature an eFPGA is a specialized version of a FPGA core that is defined by its SOC surroundings
The main impacts of DEMETER will be:
- Enhance the technical capabilities and competiveness of Europe on the worldwide concerned markets (space, automotive, avionics, transportation and energy),
- Reduce the dependence on technologies and capabilities from outside Europe,
- Enable the European industry to get a non-restricted access to high performance technologies,
- Improve the overall European space and avionic technology landscapes.