ESA have presented their work on “Implementation of Vision algorithms on BRAVE FPGA’s developed in MATLAB and VHDL environment” at the SpacE FPGA Users Workshop (SEFUW 2018) at ESA/ESATEC, 9th-11th April 2018

ESA have presented their work on “Implementation of Vision algorithms on BRAVE FPGA’s developed in MATLAB and VHDL environment” at the SpacE FPGA Users Workshop (SEFUW 2018) at ESA/ESATEC, 9th-11th April 2018

Details: https://indico.esa.int/indico/event/232/session/6/contribution/15/material/slides/0.pdf

DEMETER First Year Review Meeting

The first year review meeting of the DEMETER project took place on 6th of October 2016 in Paris, France.

It was an opportunity for the consortium members to present their achievements during Year 1 and to define the activity planned for Year 2.

DEMETER Website now online!

The DEMETER Consortium is pleased to officially announce the launch of the project’s official webpage on the 30th of April 2016.
Our goal with this website is to provide our visitors an easier way to learn about DEMETER project, its developments, consortium and the progress in research!

DEMETER kick-off meeting

The kick-off meeting of the ENIAC Joint Undertaking project DEMETER took place on 3rd and 4th of November 2015 in Paris, France.
The meeting gathered consortium members in order to define a plan for research and project’s progress.